1. Field of the Invention
This invention relates to semiconductor devices. More particularly this invention relates to Metal Oxide Semiconductor (MOS) field effect transistors (FET) connected to function as a combination of a lateral bipolar transistor and an FET.
2. Description of the Related Art
The structure of an MOSFET as shown in FIG. 1 is fundamental in the implementation of integrated circuits. An n-type material is implanted to a low concentration into the surface of a p-type semiconductor substrate 100 to form an n-type diffusion well 105. A p-type material is then implanted to a low concentration into the n-type diffusion well 105 to form a p-type bulk region 110 is of the MOSFET. The p-type material is then implanted to a high concentration in the p-type bulk region 110 to form a low resistivity p-type contact 135 to the bulk electrode 150. The n-type material is further implanted to a high concentration to form the source region 115 and the drain region 120. The source region 115 is connected to the source electrode 160 and the drain region 120 is connected to the drain electrode 165.
An insulating layer generally of silicon dioxide (SiO2) is deposited on the surface of the semiconductor substrate 100 between the source region 115 and the drain region 120 above the channel region 170 to form the gate oxide 125. A conducting material such as a metal or a highly doped polysilicon is deposited on the gate oxide to form the gate 130, which is attached to the gate electrode 145.
FIG. 2a shows the energy band diagram of the MOSFET with the biasing voltage source 140 set to a voltage level of zero volts. This effectively has the p-bulk 110 is connected directly from the bulk terminal 150 to the source terminal 160 to the source 115. The energy band diagram illustrates the energy levels beginning at the n+ highly doped polysilicon gate 220 and proceeding vertically through gate oxide 225 into the p-type bulk region 240.
The energy level required for conduction within the n+ highly doped polysilicon gate 220 is the energy level E.sub.pg 215. The energy level where the number of electrons in the conduction energy band E.sub.c 235 is equal to the number of holes in the valance band is the Fermi level E.sub.f 200.
The energy levels for the conduction band and the valance band within the gate oxide 225 are very large relative to the energy levels under consideration in this Figure. The energy level of the conduction bank E.sub.c 235 begin to lower near the surface of the p-type bulk 240 and rises within the body of the p-type bulk 240. Similarly the energy level of the valance band E.sub.v 230 begins at a lower level at the surface of the p-type bulk 240 and rises within the body of the p-type bulk 240 in parallel with the energy level of the conduction band E.sub.c 235. The level of the middle of the gap between the energy level of the conduction band E.sub.c 235 and the energy level of the valance band E.sub.v 230 is the intrinsic Fermi level E.sub.i 205.
The built-in voltage of the n+ source at the junction of the n+ source 115 of FIG. 1 and the p-type bulk 110 of FIG. 1 in the area of the channel region 170 of FIG. 1 is denoted as .psi..sub.s(n+ source) 245. The amount of energy necessary to begin conduction within the p-type bulk 240 of the built-in voltage is the amount of difference of the intrinsic Fermi level .psi..sub.sp at the surface of the p-type bulk 225 and within the body of the p-type bulk 240. The threshold voltage is then a function of the built-in voltage of the n+ source .psi..sub.(n+ source) and the built-in voltage .psi..sub.sp of the p-type bulk 240.
The MOSFET as shown in FIG. 1 can be configured as shown in U.S. Pat. No. 4,089,022 (Asai et al.) and U.S. Pat. No. 4,999,518 (Dhong et al.) as what is termed in this invention as a lateral quasi-unipolar transistor. The drain region 120 is the collector, the source region 115 is the emitter of the transistor, and the p-type bulk region 110 is the base of the bipolar transistor. Both Asai et al. and Dhong et al. describe use of the gate 130 to create an FET channel voltage drop.
Asai et al. (col. 9 line 57-col. 10 line 37, FIGS. 23, 26, 29, 31) describes placing a biasing voltage source V.sub.DC 140 between the gate 130 and the base/bulk region 110. The electric field created between the gate 130 and the base/bulk region 110 will effectively create a transistor having two built-in voltages as shown in FIGS. 2b and 2c. FIG. 2b shows the energy band diagram of the MOSFET of FIG. 1 configured according to Asai et al. from the gate 220 through the gate oxide 225, and into the surface of the semiconductor substrate 240. The energy band diagram have the biasing voltage source V.sub.DC 140 set to 0 volts effectively connecting the base/bulk region 110 of FIG. 1 to the gate 130.
As is shown in FIG. 2b compared with FIG. 2a, the Fermi level E.sub.f 200 becomes flat and the energy levels of the conduction band E.sub.c 235, the valance band E.sub.v 230, and the intrinsic Fermi level E.sub.i 205 are lowered. Thus the emitter level of the built-in voltage .psi..sub.sp between the channel region at the surface of the p-type bulk 240 and the body of the p-type bulk 240 is also lowered.
FIG. 2c shows the energy levels within the n+ source 115 of FIG. 1 of the conduction band E.sub.c 250, the valance band E.sub.v(n+ source) 260, and the intrinsic Fermi band E.sub.i(n+ source) 255. The built-in voltage for the bulk .phi..sub.bi 280 is determined by the formula: EQU .phi..sub.bl =E.sub.i(pbulk) -E.sub.I(n+ source) -V.sub.1
where: PA1 E.sub.i(pbulk) is the intrinsic Fermi voltage of the body of the p-type bulk 240 of FIG. 2b. PA1 where:
E.sub.i(n+ source) is the intrinsic Fermi voltage of the n+ source of FIG. 2c.
V.sub.1 the voltage of the biasing voltage source V.sub.DC 140 of FIG. 1.
The built-in voltage at the surface .phi..sub.bis 285 is determine by the formula: EQU .phi..sub.bis =[.psi..sub.sp-.psi..sub.(n+ source) -V.sub.1 ]
.psi..sub.sp is the interface potential of the p-type bulk 240 and the body of the p-type bulk 240.
.psi..sub.s(n+ source) 275 is the interface potential of the n+ source of FIG. 2c.
It is apparent that the built-in voltage .phi..sub.bis 285 at the surface of the p-type bulk 240 and the built-in voltage .phi..sub.bis 280 of the body of the p-type bulk 240 can be lowered with an increase in the voltage level V1 of the biasing voltage source 140 of FIG. 1.
In radio frequency (RF) applications, the level of noise sources from devices and circuits determine the sensitivity of receivers. Flicker noise or 1/f noise is associated with contamination and crystal defects in the junction between the base/bulk region 110 of FIG. 1 and the emitter/source region 115 or at the surface of base/bulk region 110 in the channel region 170 at the interface of the semiconductor substrate 100 and the gate oxide 125. The more homogeneous the medium of conduction of current through the base/bulk region 110 the less the flicker noise of 1/f noise. The flicker noise or 1/f noise is thus proportional to the number of carriers passing under the gate oxide 225. Since the built-in voltage at the surface .phi..sub.bis 285 is smaller than the built-in voltage for the bulk .phi..sub.bi 280, more carriers are flowing along the surface, making the flicker noise or 1/f noise greater.